1. Field of the Invention
This invention relates to architecture of a communication subsystem used in In-Flight Entertainment Systems on aircraft. In particular, the invention relates to the use of a dual-ported RAM and a microcontroller to streamline the communication activities between peripheral subsystems and a host processor.
2. Description of Related Art
In-Flight Entertainment Systems (IFES) are now becoming popular on commercial aircraft. A typical new IFES may offer a variety of services including music, news, movies, video on demand, telephone, and games to passengers right at the passengers' seats with the convenience of individualized control. A timetable is generally provided from which a passenger may choose options when he or she requests services. Such a system involves a large number of interconnections to various peripheral subsystems. The communication between these subsystems and the main processor (or the host processor) can be quite complex. A host processor, referred to as a System Control Unit (SCU), communicates with a large number of external Line Replacement Units (LRUs) for various operational and control functions, as overhead display, video and audio control. In addition to maintaining and managing a large communication load, the host processor also has to perform its own tasks. The communication problem is even more severe when the host processor is required to process error information and/or other ancillary data as part of the communication messages.
To solve this problem, a system may employ either an interrupt or polling communication scheme. In an interrupt scheme, the peripheral subsystem generates a request signal to the host processor to interrupt the host and request service. This interrupt mechanism may be sufficient when the number of peripheral subsystems is small and the host has a relatively light workload. However, when there is a significant number of peripheral subsystems that need to communicate with the host and the host itself has to perform a large number of operations, the interrupt scheme is unsatisfactory. The host becomes overloaded with too many interrupt requests resulting in the situation that the host cannot timely respond to all requests, and/or acquire the time to perform other tasks.
In a polling scheme, the host determines whether a peripheral device needs service by checking certain status information that indicates whether a peripheral device requires service. By polling, the host is able to control when the status is checked and therefore when the service is performed. However, if the host does not check the status frequently enough, many requests may be pending concurrently thus creating a long waiting time. The problem is further compounded when the system includes a large number of devices requesting service as peripheral devices operate at slow data transfer rates.
In a typical prior art IFES architecture, the host processor interfaces to a group of Communication Interface Controllers (CICs) through the host bus. The Communication Interface Controller may be one of a variety of communication interfacing devices such as the Universal Asynchronous Receiver and Transmitter (UARTs). The CICs are connected to the corresponding external devices. If an interrupt mechanism is implemented, CICs generate interrupt signals which usually go to an interrupt controller. The interrupt controller resolves the priority and processes the interrupt requests to produce a host interrupt signal connected to the interrupt request of the host processor. The host processor and the external devices may exchange messages using an interrupt or polling mechanism. Both the interrupt and polling schemes operating in this manner have the following disadvantages:
1) The host spends too much time checking the status (for polling) or responding to interrupt service routines. When the number of external devices increases or the size of the messages is large, the host is busy communicating with these devices and does not have the time to perform its own tasks. PA1 2) The CIC itself can only either transmit or receive, not both simultaneously because the host can only read or write at any point in time. Therefore, when the host and the external device send messages to each other, there will be some delay or a buffering mechanism is needed to temporarily store the messages.
The above disadvantages result in degraded performance of the IFES. A passenger in a crowded aircraft, for example, may perceive slow responses to his or her requests. A video program may be interrupted frequently. An on-going game may be suspended.
It is therefore desirable to have a system to act as a communication handler which manages the communication load to relieve the burden from the host processor and at the same time can process the messages to and from the host in an efficient manner.